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SN74LS166 8-Bit Shift Registers
The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
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LOW POWER SCHOTTKY
16 1
* Synchronous Load * Direct Overriding Clear * Parallel to Serial Conversion
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA
16
PLASTIC N SUFFIX CASE 648
1
SOIC D SUFFIX CASE 751B
ORDERING INFORMATION
Device SN74LS166N SN74LS166D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS166/D
SN74LS166
PARALLEL PARALLEL INPUTS F 11 F E 10 E CLEAR 9
SHIFT/ INPUT OUTPUT G H QH VCC LOAD 16 15 SHIFT/ LOAD 14 H 13 QH 12 G
SERIAL INPUT A 1 SERIAL INPUT 2 A B 3 B C 4 C D 5 D
CLEAR CLOCK INHIBIT CK 8 6 7 CLOCK CLOCK GND INHIBIT
PARALLEL INPUTS
FUNCTION TABLE
INPUTS CLEAR L H H H H H SHIFT/ LOAD X X L H H X CLOCK INHIBIT X L L L L H PARALLEL CLOCK X L SERIAL A...H X X X H L X X X a...h X X X QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 INTERNAL OUTPUTS OUTPUT QH
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SN74LS166
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD A B C PARALLEL INPUTS D E F G H OUTPUT QH SERIAL SHIFT CLEAR (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A
R CK S
H L H L H L H H INHIBIT LOAD HH L HLHL SERIAL SHIFT H
QA B (3)
R S
CK
QB C (4)
R S
CK
QC D (5)
R S
CK
QD E (10)
R S
CK
F
(11)
R
QE
CK
S
QF (12) G
R CK S
QG H CLOCK CLOCK INHIBIT (14) (7) (6)
R S
CK
(13) Q H
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SN74LS166
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 38 0.5 20 V A mA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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SN74LS166
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT FOR TEST H Serial Input SHIFT/LOAD 0V 4.5 V OUTPUT TESTED QH at tn+1 QH at tn+8
AC WAVEFORMS
tw(clear) CLEAR INPUT Vref Vref 0V tn CLOCK INPUT Vref tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref tsu tn + 1 (SEE NOTE 1) tn tn + 1 3V Vref th Vref tsu Vref th Vref 0V tPHL (clear-Q) Vref tPHL (CLK-Q) VOH Vref
NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V.
3V
0V 3V
tPLH (CLK-Q)
OUTPUT Q
Vref VOL
AC CHARACTERISTICS (TA = 25C)
Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Clear to Output Clock to Output Min 25 Typ 35 19 23 24 30 35 35 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF F Test Conditions
AC SETUP REQUIREMENTS (TA = 25C)
Limits Symbol tW ts ts th Parameter Clock Clear Pulse Width Mode Control Setup Time Data Setup Time Hold Time, Any Input Min 30 30 20 15 Typ Max Unit ns ns ns ns VCC = 5 0 V 5.0 Test Conditions
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SN74LS166
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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SN74LS166
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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SN74LS166
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SN74LS166/D

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